G - Physics – 06 – F
Patent
G - Physics
06
F
354/233
G06F 13/38 (2006.01) H04L 13/14 (2006.01)
Patent
CA 1241126
ABSTRACT A circuit for transmitting data signals to a plurality of ports designated by predetermined address signals. The circuit is comprised of a plurality of addressable latches having address inputs thereof connected together and corresponding lines of an address bus for carrying the address signals. Each of the latches has a data input thereof connected to a predetermined corresponding line of data bus for carrying the data signal, and a plurality of data outputs thereof connected to respective terminals of corresponding ones of the aforementioned ports. The latches receive the address signals on the address inputs thereof such that data signals appearing on the data inputs are transmitted so as to appear on a predetermined output thereof for transmission to the corresponding port. According to a preferred embodiment, the circuit also includes a master address decoding circuit for receiving the address signals and generating a enable signal in response thereto for application to an enable control input of each of the latches. The use of addressable latches for the transmission of data signals results in very little circuit board tracking and significantly less cost relative to expensive octal latches.
496404
Mitel Corporation
Shapiro Cohen
LandOfFree
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