Fifo memory with decreased fall-through delay

Details Fifo memory with decreased fall-through delay Fifo memory with decreased fall-through delay

G - Physics

06

F

354/241, 328/44

G06F 5/06 (2006.01) G06F 5/08 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1263195

ABSTRACT OF THE DISCLOSURE A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled to a bypass bus. Data is introduced on the bypass bus, and control logic writes the data into the section nearest the output which is currently not full. The individual register stages are self-clocked, so that data is then shifted toward the output through any vacant registers. In another aspect, the register stages are arranged in sections of different length, with the shortest section closest to the output and the longest section closest to the input. Decreased fall-through delay is achieved by minimizing the length of the FIFO buffer actually traversed by the data while insuring that the order of the data remains unchanged.

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