G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.73
G06F 9/32 (2006.01)
Patent
CA 1194605
ABSTRACT The invention is an information handling apparatus of the type compri- sing a memory, a circuit for designating a memory location where the instruction to be read is stored, a circuit for reading the designated instruction out of the memory, a circuit for detecting that a predetermined instruction has been read out and generating a detection signal and a circuit for inhibiting execu- tion of at least one subsequently scheduled instruction in response to the detection signal. According to prior techniques up to several machine cycles of time are required to read out the instruction to be inhibited and the same time is required to exchange the instruction with a non-operation instruction. According to the invention a circuit is provided for preparing in a short period of time an address for a next new instruction of the inhibited instruction. Thus the invention replaces the address of an instruction which is not to be executed with the address of the next instruction to be executed. The pro- cessing time is thereby greatly shortened.
390879
Nippon Electric Co. Ltd.
Smart & Biggar
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