G - Physics – 06 – F
Patent
G - Physics
06
F
354/237
G06F 12/08 (2006.01) G06F 13/16 (2006.01)
Patent
CA 1286790
Abstract of the Disclosure A memory access control apparatus has a plurality of request reception sections, respectively connected to a plurality of units for supplying requests, for receiving a block read request from the corresponding units, and dividing the block read request into a plurality of read requests and outputting the divided read requests, a selector for selecting one of outputs from the request reception sections and outputting the selected output, a request processing section for processing the request output from the selector and outputting reply data to a corresponding unit, and a main memory connected to the request processing section. The request reception section has a counter for counts the read requests of the block read request and outputting the obtained count to the request processing section through the selector, and the request processing section has a miss detecting circuit for detecting a miss during processing of a block read request, a determining circuit for determining by an output from the counter the number of replies to be supplied to the unit that has sent the request when the miss detecting circuit detects a miss, and a circuit for receiving an output from the miss detecting circuit and outputting to the request reception section a signal for invalidating requests following the block read request, among the plurality of read requests, in which a miss has occurred.
552298
Corporation Nec
Smart & Biggar
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