Flexible imbedded test system for vlsi circuits

Details Flexible imbedded test system for vlsi circuits Flexible imbedded test system for vlsi circuits

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G01R 31/3185 (2006.01) G06F 11/267 (2006.01)

Patent

CA 1290017

ABSTRACT OF THE DISCLOSURE A logic chip contains a plurality of ranks of flip- flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in para- llel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. The system provides for an on-chip maintenance test system that is adaptable to custom or semi-custom VLSI chip design and it teaches that any "component" (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data). The test data output can be transmitted in parallel between the flip-flop ranks, or it can go serially through the flip-flop components of a given rank.

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