Semiconductor integrated circuits gettered with phosphorus

Details Semiconductor integrated circuits gettered with phosphorus Semiconductor integrated circuits gettered with phosphorus

H - Electricity

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H01L 21/322 (2006.01) H01L 21/316 (2006.01) H01L 21/768 (2006.01) H01L 21/82 (2006.01) H01L 21/8234 (2006.01)

Patent

CA 1226073

- 14 - SEMICONDUCTOR INTEGRATED CIRCUITS GETTERED WITH PHOSPHORUS Abstract For achieving dense packing of MOS transistors at the top surface of a silicon semiconductor body, second level metallization including arsenic doped polysilicon contacts are used in conjunction with a phosphorus gettering step at a time when the top surface is sealed against the introduction of phosphorus by an undoped sacrificial glass layer, i.e., which is essentially free of phosphorus. The second level metallization is thereafter completed by coating the polysilicon with a high conductivity metal, such as aluminum. During the gettering, the polysilicon contacts are insulated from the first level metallization by a planarized glass layer doped with phosphorus to a concentration below the saturation level of phosphorus in the glass.

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