Pipeline error correction

Details Pipeline error correction Pipeline error correction

G - Physics

06

F

354/223.1

G06F 11/08 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1213674

Abstract of the Disclosure In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory- control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error- correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non- redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct. If the memory-control circuitry (30) determines that a word that it has forwarded to the processor (10) is incorrect, it immediately fetches the corresponding error-correction code and corrects the location in memory. Then, when the processor (10) finds that the parity is incorrect in the data word, it repeats its request for the data word in question, which the memory-control circuit (30) has corrected in the memory (32).

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