Stud-defined integrated circuit structure and fabrication

H - Electricity – 01 – L

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H01L 27/04 (2006.01) H01L 21/033 (2006.01) H01L 21/308 (2006.01) H01L 29/06 (2006.01)

Patent

CA 1238117

Abstract Disclosed is a process of fabricating a submicron wide single crystal silicon structure protruding from a monolithic silicon body. Starting with a single crystal N silicon body having a P region, an insulator stud of sub micron width and length dictated by the limits of lithography is formed on the P region. Using the stud as a mask, the P region is etched forming the top narrow portion having the stud width projecting from the silicon body. On the exposed sides of the top portion oxide walls are formed and the etching continued forming the middle portion of a width exceeding that of the top portion. An oxide-nitride wall is established on the exposed sides of the middle portion and, using the resulting structure as a mask, the etching is continued to completely etch through the P region and a substantial portion of the underlying N silicon body thereby forming a free-standing silicon protrusion structure. Thick oxide walls are formed on the just exposed sides of the silicon.

502055

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