Digital data receiver including timing adjustment circuit

Details Digital data receiver including timing adjustment circuit Digital data receiver including timing adjustment circuit

H - Electricity

04

B

325/72

H04B 1/16 (2006.01) H04L 7/027 (2006.01) H04L 7/10 (2006.01) H04L 27/22 (2006.01) H04L 27/38 (2006.01)

Patent

CA 1222289

Digital Data Receiver Including Timing Adjustment Circuit Abstract of the Invention Digital Data receiving apparatus includes means for adjusting the timing of the sampling in- stants. A phase controlled oscillator (PCO 19) pro- vides timing signals for sampling the received signal and is controlled, at the commencement of a received signal, by a timing initialization circuit (17) re- sponsive to repetitive phase alterations in a training sequence. The timing initialization circuit (17) includes a plurality of Discrete Fourier Transform (DFT) circuits (23) responsive to frequencies depen- dent on the power spectral densities of the received signal, which received signal may be modulated at a normal rate or a fall-back rate. The DFT circuits (23) measure the correlation of locally-generated frequencies with the incoming samples for a predeter- mined number of such samples to produce a plurality of complex signals. A selector circuit (24) selects a pair of the complex signals dependent on the modula- tion rate. The provided pair of complex signals are multiplied in a complex conjugate multiplier (25) to produce a complex output signal which is fed to a phase segment detector (26) to provide a complex rotated signal. The complex rotated signal is con- verted in a phase-to-time-shift converter circuit (27) to a signal (m) for controlling the PCO 19.

471888

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