Pre-fetch circuit for a corrective memory

Details Pre-fetch circuit for a corrective memory Pre-fetch circuit for a corrective memory

G - Physics

06

F

354/224

G06F 11/28 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1188813

-13- CIRCUIT FOR REUSING PREVIOUSLY FETCHED DATA Abstract A memory addressing system includes an address- able memory provided with error checking and correction (ECC) circuits which include output latches adapted to latch corrected data read from the memory. An applied memory address is compared in a comparator with a prev- ious memory address stored in an address latch and if a match is detected, a match signal is effective to inhibit the occurrence of the next memory cycle and to activate a decoder coupled to the output of the ECC circuits to cause transfer to the system bus of selected data from the ECC latches. If no match is detected, a memory cycle is initiated to access the desired data in the mem- ory. A high-speed memory operation is thus achieved utilizing simple circuitry.

427802

Affiliated with

Also associated with

Rating

Pre-fetch circuit for a corrective memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pre-fetch circuit for a corrective memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pre-fetch circuit for a corrective memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1281967