Multi-processor system

Details Multi-processor system Multi-processor system

G - Physics

06

F

354/233

G06F 13/36 (2006.01) H04L 12/417 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 1209713

ABSTRACT A multi processor system in which processors communicate via a bus with ordered access of the processors to the bus. After receipt of a trigger signal each triggered processor times its access to the bus dependent on its unique code (which may be its address) and the function the processor is to perform. In a special case in a first phase several processors transmit information along the bus in a queued manner to a receiving processor which infers the processor transmitting the information it is reading from the time lapse from the trigger signal; in a second phase a processor transmits information onto the bus in a queued manner and each receiving processor by timing its reading of the bus reads the information intended for it. An application of the invention in intra-shelf communication in a private branch telecommunications exchange is described.

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