Scan operation for a central processor

Details Scan operation for a central processor Scan operation for a central processor

H - Electricity

04

Q

354/233, 344/29

H04Q 3/54 (2006.01) G06F 9/308 (2006.01)

Patent

CA 1064149

ABSTRACT A central processor of the type which controls the operation of telephone exchange sysbsystems to establish requested service between telephone subscribers in response to a plurality of addressable multiple bit operational codes wherein each of the subsystems is connected to the central processor by a common data bus and assigned a discrete sub- system address for enabling the addressing of each subsystem and wherein one of the subsystems is a program memory contain- ing the plurality of operational codes has a scan means for locating stored subsystem data which contains preselected bits of data responsive to a particular operational code which includes first and second partial subsystem addresses and a mode bit for specifying either a direct scar. mode or an indirect scan mode. In the direct scan mode a combining means combines the first partial address with a third partial address stored in one of the central processor stores to provide a composite subsystem address. A bus address register addresses the sub- system having the composite address and obtains the data stored therein. A comparator compares the stored subsystem data to a compare constant consisting of the preselected bits of data. If they are identical the scan means is terminated and if they are not identical the third partial address is incremented to the next subsystem address to be interrogated. In the indirect mode the combined first and third partial addresses are an address obtaining composite address and the data received is an address word. The combining means combines the address word and the second partial subsystem address to obtain the composite subsystem address for locating the preselected bits of data.

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