High density multi-layer printed circuit arrangement

Details High density multi-layer printed circuit arrangement High density multi-layer printed circuit arrangement

H - Electricity

05

K

356/16

H05K 1/02 (2006.01)

Patent

CA 1229179

A HIGH DENSITY MULTI-LAYER PRINTED CIRCUIT ARRANGEMENT ABSTRACT An arrangement for constructing multi-layered printed circuits characterized by a first layer having top and bottom surfaces with the top surface including a plurality of parallel conductors. The bottom surface further includes a plurality of parallel conductors arranged perpendicular to the conductors on the top surface. A plurality of holes extend through the first layer, with each hole adjacent to an intersecting conductor pair. A second layer including top and bottom surfaces and a plurality of plated through holes has conductor pennants extending from selected holes in a first direction on the top surface and a second opposite direction on the bottom surface. A plurality of first and second layers are sandwiched together, with each hole of each layer in registration with the other and each included conductor pennant contacting a respective first layer conductor. Additionally, two or more second layers are interconnected by via pins extending through the arrangement.

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