Method and apparatus for addressing a memory by array...

Details Method and apparatus for addressing a memory by array... Method and apparatus for addressing a memory by array...

G - Physics

06

F

354/233

G06F 12/02 (2006.01) G06F 12/06 (2006.01)

Patent

CA 1264093

Abstract of the Disclosure A memory having an address generator in an intelligent port which generates address sequences specified by an array transformation operator in a programmable processor, thereby allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a present instruction. The intelligent port of the memory creates complex data structures from input data arrays stored in memory and directs the trans- formation of the data structures into output data streams. The memory comprises a plurality of read-write memory banks and a bank of read-only memory interconnected through in- telligent ports and busses to other units of the processor. An arbitration and switching network assigns memory banks to the intelligent ports.

583309

Affiliated with

Also associated with

Rating

Method and apparatus for addressing a memory by array... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for addressing a memory by array..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for addressing a memory by array... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1284712