Buffer memory control system

Details Buffer memory control system Buffer memory control system

G - Physics

06

F

354/237

G06F 12/08 (2006.01)

Patent

CA 1250053

BUFFER MEMORY CONTROL SYSTEM ABSTRACT OF THE DISCLOSURE A buffer memory control system for executing an immediate instruction, comprising a block fetch control unit for generating a first move-in complete signal indicating that the move-in of the heading subblock from a main memory to the buffer memory is completed. In response to the first move-in complete signal, the fetch and store operation starts without waiting for the completion of the move-in of a full block.

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