Memory testing system

Details Memory testing system Memory testing system

G - Physics

11

C

354/225, 352/82.

G11C 29/00 (2006.01) G06F 11/28 (2006.01) G11C 29/40 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1315886

ABSTRACT A DRAM test system includes a storage location tester and controller tester. The storage location tester utilizes an error correction code which generates redundancy symbols corresponding to inverted data that are the binary inverse or compliment of the redundancy symbols corresponding to the non- inverted data. Thus each bit-location of an addressable storage location, consisting of both data and ECC redundancy bit locations, can be fully tested for storage and retrieval of both a ONE and a ZERO in only three read/write cycles. The controller tester tests the DRAM controller circuitry by sequencing it through various operations, at least one of which is a refresh operation. When a refresh operation occurs the node signals corresponding to the refresh operation are incorporated into a DRAM controller signature vector. To counter the effects of the refresh operation on the signature vector, a refresh-vector is applied to the signature vector register during the refresh operation and the contents of the register are updated. This results in the contents of the signature vector being "returned" to the pre-refresh contents at the end of a properly executed refresh. At the completion of the testing cycle the signature vector may then be compared with the expected output vector, which does not include any refresh operation information, to determine if the DRAM is functioning properly.

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