G - Physics – 06 – F
Patent
G - Physics
06
F
354/1
G06F 9/46 (2006.01) G06F 17/12 (2006.01) G06F 17/16 (2006.01) G06F 17/50 (2006.01)
Patent
CA 1276296
ABSTRACT Disclosed is a method for use in a computing apparatus employing a plurality of central processing units (CPUs) oper- ating in parallel, and a shared memory shared by the CPUs, and wherein the plurality of CPUs are operated to create a matrix utilized to solve complex multivariable circuit equations for the purpose of circuit simulation evaluation, with the matrix entries assigned according to a matrix of circuit nodes. The method avoids the need for synchronization of the access to the shared memory by the plurality of CPUs and comprises the steps of: determining the number of circuit elements connected to each node corresponding to a matrix entry; assigning a plurality of dis- tinct memory locations to each matrix entry according to the number of circuit elements connected to the node corresponding to the matrix entry, with each memory location assigned to a specific circuit element; directing the CPUs to write into the respective memory location associated with a respective circuit element connected to the respective node when operating on the contri- bution of the respective circuit element to the matrix entry associated with the respective node.
544993
Bischoff Gabriel P.
Greenberg Steven S.
Bischoff Gabriel P.
Digital Equipment Corporation
Greenberg Steven S.
Smart & Biggar
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