Test system for random access memory

Details Test system for random access memory Test system for random access memory

G - Physics

11

C

354/224

G11C 29/00 (2006.01) G11C 29/50 (2006.01) G01R 31/3193 (2006.01)

Patent

CA 1287409

TEST SYSTEM FOR RANDOM ACCESS MEMORY ABSTRACT OF THE DISCLOSURE A test system for a random access memory includes: a clock pulse width varying unit for varying a pulse width of driving pulses for a random access memory; a first latch connected to an address input circuit of the random access memory for receiving the output clock signal fo the clock pulse width varying unit and latching an address input signal at the leading edge of the output clock signal; and, a second latch connected to a data output circuit of the random access memory for latching a data output signal. Both the first and second latches are supplied with the same clock signals from the clock pulse width changing unit, and a comparison unit is connected to a data output circuit of the random access memory for comparing the output of the random access memory with a predetermined expectation value. The output of the comparison unit is latched by the trailing edge of the clock pulse in the second latch.

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