Temperature compensation for semiconductor logic gates

Details Temperature compensation for semiconductor logic gates Temperature compensation for semiconductor logic gates

H - Electricity

03

K

328/139

H03K 19/003 (2006.01) H03K 19/094 (2006.01)

Patent

CA 1267940

ABSTRACT A temperature compensation system for semiconductor logic gates where the temperature compenstation is accomplished by two depletion mode FET's in electrical series relationship is disclosed. One of the FET's is adapted to operate in its triode region of operation and the other in its saturation region of operation.

521787

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