G - Physics – 11 – C
Patent
G - Physics
11
C
352/37.3
G11C 19/08 (2006.01) G11C 11/14 (2006.01)
Patent
CA 1182917
ABSTRACT OF THE DISCLOSURE This invention uses a plurality of bubble memory chips in a system for providing simultaneous input and output in a word or byte organized out- put. Each bubble memory chip has the same number of minor loops as is required for nominal memory size without the requirement for extra or redundant loops. Each bubble memory chip may have a number of faulty minor loops where the bit output is incorrect and cannot be used. However, a requirement for this system is that no two bubble memory chips may have a faulty bit or minor loop at the same major loop address location. An additional bubble memory chip is provided which will contain the correct data bits for locations corresponding to de- fective major loop addresses in the bubble memory chips making up the byte. A Programmable Read Only Memory (PROM) is provided and connected with a logic network to control the gating of the outputs of the bubble memory chips associ- ted with the memory byte and the extra bubble memory chip to control the gating of the outputs. Thus, as contents of the various bubble memory chips are ad- dressed, the PROM controls the gating of the bits forming the output byte or word so that the output byte or word is comprised of only correct bits.
359132
Control Data Corporation
Smart & Biggar
LandOfFree
Memory system using faulty bubble memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory system using faulty bubble memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory system using faulty bubble memory devices will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1305102