Level detecting circuit

G - Physics – 01 – R

Patent

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Details

328/174, 330/39,

G01R 19/165 (2006.01) H03G 1/00 (2006.01) H03G 7/00 (2006.01)

Patent

CA 1172710

ABSTRACT OF THE DISCLOSURE A level detecting circuit for use in a noise reduction circuit and which produces a level detected output signal in response to an input signal, includes an operational amplifier with at least one feedback diode for logarithmically converting the input signal to produce a logarithmically converted signal; a first PN junction element comprised of a first diode supplied with the logarithmically converted signal; a second PN junction element comprised of a second diode connected in series with the first diode at a connection point, the series-circuit of the first and second diodes having a first saturation current; a first integrating capacitor having a first capacitance and connected to the connection point for producing an integrated signal; a third PN junction element comprised of series-connected third and fourth diodes connected in parallel with the series connection of the first and second diodes and having a second saturation current greater than the first saturation current; a second integrating capacitor having a second capacitance less than the first capacitance and connected to the second and fourth diodes; a reference current source for providing a reference current to the series-connected first and second diodes and series-connected third and fourth diodes, and an output circuit for producing the level detected output signal in response to the integrated signal, such that, upon an abrupt attenuation of the input signal, the level of the level detected output signal is maintained for a predetermined time to substantially eliminate low frequency band harmonic distortion.

399439

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