Method of manufacturing semiconductor device

H - Electricity – 01 – L

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H01L 21/34 (2006.01) H01L 21/027 (2006.01) H01L 21/338 (2006.01)

Patent

CA 1206626

- 1 - Abstract In manufacturing a field effect transistor, a pattern which has a wider upper layer and a narrower lower layer is formed at a gate electrode position. Using the pattern as a mask, first and second impurity regions are formed on both sides of a gate region by ion implantation. Subse- quently, at least the lower layer is buried in a material, such as an organic high polymer material, having a selec- tivity in etching characteristics with respect to the pattern material. After removing the lower layer, an electrode material is embedded in the resulting hole to form a gate electrode. The result is a method that, while using conventional photolithography, enhances fabrication at the submicron level and achieves improved accuracy of alignment.

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