Computer bus interpolator

G - Physics – 06 – F

Patent

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354/232

G06F 13/20 (2006.01) G06F 13/16 (2006.01) H04L 5/22 (2006.01)

Patent

CA 1195781

- 22 - Abstract A microcomputer having a time multiplexed bus for transferring information to and from registers and input/output ports. The bus structure includes a large capacity address bus, a data bus, a two phase clock, and interpolator circuitry connected between the address bus and data bus so that during one clocK phase signals derived in part from the address bus are placed on the data bus in order to reference particular registers or input/output ports, and during a second clock phase signals are transferred to the selected register or input/output port from the data bus.

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