Serial-parallel-serial charge coupled device and method of...

Details Serial-parallel-serial charge coupled device and method of... Serial-parallel-serial charge coupled device and method of...

G - Physics

11

C

352/82.2

G11C 11/40 (2006.01) G11C 27/00 (2006.01) H01L 29/76 (2006.01)

Patent

CA 1187177

SERIAL-PARALLEL-SERIAL CHARGE COUPLED DEVICE MEMORY AND METHOD OF TRANSFERRING CHARGE THEREIN Abstract of the Disclosure An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and rirst storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage gate of the output register in response to the high speed clock signals of the output serial register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

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