Computer bus having page mode memory access

Details Computer bus having page mode memory access Computer bus having page mode memory access

G - Physics

06

F

354/237

G06F 13/16 (2006.01) G11C 7/10 (2006.01) G11C 8/12 (2006.01) G11C 11/406 (2006.01)

Patent

CA 1304523

ABSTRACT Method and apparatus are disclosed for use in a digital computer system having a system bus for interconnecting together various agents. A page mode type of memory access provides for the rapid transmission of a block of data across the bus. Blocked refresh means is also employed which disables, if possible, the burst refresh of the memory until a data transfer is completed. A local processor upon an agent having a memory controlled in such manner is provided a high priority signal line for overriding a current bus transfer for gaining access to the memory. During such a high priority access the blocked refresh means operates in a manner somewhat similar to its operation during the sequential bus transfer, however fewer rows are refreshed during the burst refresh.

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