Method of fabrication of dielectrically isolated cmos device...

Details Method of fabrication of dielectrically isolated cmos device... Method of fabrication of dielectrically isolated cmos device...

H - Electricity

01

L

356/142

H01L 21/306 (2006.01) H01L 21/762 (2006.01) H01L 21/8238 (2006.01) H01L 29/04 (2006.01)

Patent

CA 1186808

- 14 - ABSTRACT A method of fabricating an integrated circuit on a body of semiconductor material having a major surface layer of (110) crystallographic orientation by etching vertical slots into the layer to form distinct islands; depositing dopant species in predetermined ones of the silicon islands so that the major surface and exposed edges of ones of the islands become second conductivity type; and thermally oxidizing the exposed surface portions of the body so that oxide fills the vertical slots between the islands.

407810

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