Data processing system bus architecture

Details Data processing system bus architecture Data processing system bus architecture

G - Physics

06

F

354/234

G06F 13/36 (2006.01) G06F 13/40 (2006.01)

Patent

CA 1318037

ABSTRACT An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.

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