Direct memory access interface arrangement

Details Direct memory access interface arrangement Direct memory access interface arrangement

G - Physics

06

F

354/237

G06F 13/16 (2006.01) G06F 13/28 (2006.01)

Patent

CA 1194608

- 23 - DIRECT MEMORY ACCESS INTERFACE ARRANGEMENT Abstract For use in a data communication channel for transferring data between a host processor and a remote data center, the disclosed direct memory access interface arrangement comprises an input and an output register, a direct memory access interface controller, and a host access buffer for loading a peripheral processor program into a random access memory. Connected between the data and address buses of a peripheral unit, the host access buffer transfers controller address signals from the host processor on the data bus to the address bus to write an initial memory address and program word count into registers of the controller. In response to write orders from the host processor, the controller uses the initial memory address and program word count to address locations in the memory in which the peripheral processor program may be loaded.

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