Memory array

Details Memory array Memory array

G - Physics

06

F

354/237, 354/246

G06F 12/06 (2006.01) G06F 1/03 (2006.01)

Patent

CA 1227884

ABSTRACT A memory array includes a pair of memories of which the one is always synchronously addressable by a cyclical addressing means, the other memory being synchronously addressable during a read phase by the cyclical address in means, and asynchronously addressable by an externally connectable address bus during a write phase, the one memory being in a write phase writing data read from the other memory whilst the latter is in its read phase, and otherwise in a read phase, whereby one memory is always available for the cyclical reading of data.

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