Apparatus and method for testing and verifying the refresh...

Details Apparatus and method for testing and verifying the refresh... Apparatus and method for testing and verifying the refresh...

G - Physics

11

C

354/224, 352/41,

G11C 29/00 (2006.01) G11C 29/02 (2006.01)

Patent

CA 1226942

ABSTRACT OF THE DISCLOSURE The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.

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