G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 7/10 (2006.01)
Patent
CA 2608106
A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
Réseaux de mémoire à plusieurs cellules de mémoire, recevant chacune une ligne de bits, une première ligne de mots et une seconde ligne de mots. Chaque cellule comprend un circuit de sélection de cellule et aussi un commutateur à deux bornes conductrices en contact avec un article à nanotubes. Le type de réseau de mémoire décrit comprend en outre un circuit d'exploitation de mémoire relié opérationnel aux trois lignes susmentionnées de chaque cellule. Le circuit peut sélectionner la cellule par activation d'une ligne appropriée et il peut appliquer des stimuli électriques appropriés pour une modification en reprogrammation de la résistance relative de l'article entre les deux bornes. La résistance relative correspond à un état d'information de la cellule.
Bertin Claude L.
Guo Frank
Huang X.m. Henry
Konsek Steven L.
Meinhold Mitchell
Nantero Inc.
Smart & Biggar
LandOfFree
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