Bus transceiver with binary data transmission mode and...

H - Electricity – 04 – L

Patent

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H04L 5/14 (2006.01) G06F 13/14 (2006.01) H04B 1/38 (2006.01) H04B 3/50 (2006.01) H04L 12/40 (2006.01)

Patent

CA 2158155

The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmis- sion scheme for the full duplex trans- fert of control signals. In one em- bodiment of the present invention, the above-noted transfer modes are imple- mented in a bus architecture which in- cludes at least a first communications node coupled to a second communi- cations node via a twisted pair, serial bus. Each node comprises first trans- ceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal cur- rent amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control trans- fer phases and logic means for combining the resultant current amplitudes on the bus with the signal states driven by the local transceiver to output reconstructed control signals representing the control signals driven on the bus by the corresponding transceiver. Furthermore, both transceivers further include a preemptive signaling receiver for the detection of preemptive control messages which act to terminate the data transfer phases upon receipt of the message so that higher priority control transfers may take place.

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