Data bus memory circuit

Details Data bus memory circuit Data bus memory circuit

G - Physics

11

C

G11C 7/10 (2006.01)

Patent

CA 2314248

A self-locking memory circuit for a tri state data bus having multiple bit lines. The circuit includes a non-inverting buffer chip for connection to each bit line and a resistor having a predetermined electrical resistance connected across the buffer chip. The chip and resistor provide a predetermined impedance to the flow of electrical current in the self-locking circuit. The circuit changes its state when the current of the latest information on a bit line builds or lowers above or below threshold levels of the self-locking circuit.

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