Fsk demodulator using a super linear integrator

H - Electricity – 04 – L

Patent

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H04L 27/156 (2006.01)

Patent

CA 2305425

A method of and apparatus for decoding an encoded signal are disclosed. A first bit of the encoded signal is received and integrated with a super linear integrator (502) to provide a first integration signal (120, 122). A first reference signal (130) is provided as a function of a previous integration signal (126) associated with a previous bit of the encoded signal by multiplying the previous integration signal by an amount greater than one if the previous bit has a first value, and by multiplying the previous integration signal by an amount less than one if the previous bit has a second value. The first integration signal (120) is compared to the first reference signal (130) and a first bit of an output signal (142) is provided based upon the comparison. The first bit of the output signal is indicative of information encoded in the first bit of the encoded signal.

L'invention concerne un procédé et un dispositif permettant de décoder un signal codé. Un premier bit du signal codé est reçu et intégré au moyen d'un intégrateur ultra-linéaire (502), de manière à fournir un premier signal d'intégration (120, 122). Un premier signal de référence (130) est fourni en fonction d'un signal d'intégration précédent (126) associé à un bit précédent du signal codé : à cet effet, on multiplie le signal d'intégration précédent par un élément supérieur à un si le bit précédent a une première valeur, et par un élément inférieur à un si le bit précédent a une seconde valeur. Le premier signal d'intégration (120) est comparé au premier signal de référence (130), et un premier bit de signal de sortie (142) est fourni d'après la comparaison. Le premier bit du signal de sortie donne une indication sur l'information codée dans le premier bit du signal codé.

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