Multiple instruction issue computer architecture

Details Multiple instruction issue computer architecture Multiple instruction issue computer architecture

G - Physics

06

F

354/230.72

G06F 9/28 (2006.01) G06F 9/22 (2006.01) G06F 9/26 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2016068

A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decade result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

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