Firmware controlled transmit datapath for high-speed packet...

Details Firmware controlled transmit datapath for high-speed packet... Firmware controlled transmit datapath for high-speed packet...

H - Electricity

04

L

H04L 12/56 (2006.01)

Patent

CA 2236188

A datapath packet transmission controller which includes a central processing unit (CPU), a transmit FIFO buffer operative to receive and temporarily store data packets, and a disposition FIFO buffer coupled to said CPU for holding packet disposition commands received from said CPU. The CPU controls reception and storage of data packets in the transmit FIFO buffer, accesses data in data packets in the transmit FIFO buffer, provides disposition commands which control the disposition of packets after storage in the transmit FIFO buffer.

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