Digital radio receiver having amplitude limiter and...

Details Digital radio receiver having amplitude limiter and... Digital radio receiver having amplitude limiter and...

H - Electricity

04

B

H04B 1/16 (2006.01) H03G 3/20 (2006.01) H03G 7/00 (2006.01) H04B 1/30 (2006.01)

Patent

CA 2054173

In a digital radio receiver, an amplitude limiter circuit is included for producing a constant-amplitude IF signal from a received digitally-modulated IF signal. An orthogonal detector orthogonally mixes the constant-amplitude signal with a reference carrier and produces an in-phase baseband signal and a quadrature-phase baseband signal. The baseband signals are converted to first and second digital signals and supplied to respective multipliers. A logarithmic detector circuit is coupled to the amplitude limiter for generating a signal representative of the amplitude of the received IF signal. The logarithmic scale of the amplitude signal is converted to linear scale by a logarithmic-to-linear converter circuit and supplied to the multipliers in which it is multiplied with the digital baseband signals. The outputs of the multipliers are coupled to an equalizer for eliminating bit errors. The outputs of the equalizer are then directed to the demodulator for recovering the modulating signal.

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