H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 29/15 (2006.01) H01L 21/336 (2006.01) H01L 21/8234 (2006.01) H01L 29/10 (2006.01)
Patent
CA 2612123
A semiconductor device may include a strained superlattice layer (325) including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
La présente invention concerne un dispositif à semi-conducteur pouvant comprendre une couche à hétérostructure contrainte (325) dotée d~une pluralité de groupes de couches superposés qui est recouverte d~une couche de contrainte. Chaque groupe de couches de la couche à hétérostructure contrainte peut comporter une pluralité de monocouches semi-conductrices de base superposées définissant une section semi-conductrice de base, et au moins une monocouche non semi-conductrice contrainte au sein d~un réseau cristallin de sections semi-conductrices de base adjacentes.
Kreps Scott A.
Mears Robert J.
Mears Technologies Inc.
Teitelbaum & Maclean
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