Very low voltage inter-chip cmos logic signaling for large...

Details Very low voltage inter-chip cmos logic signaling for large... Very low voltage inter-chip cmos logic signaling for large...

H - Electricity

01

L

H01L 27/092 (2006.01) H01L 23/60 (2006.01) H03K 3/3565 (2006.01) H03K 17/0814 (2006.01) H03K 17/16 (2006.01) H03K 19/003 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 2113987

ABSTRACT OF THE DISCLOSURE A CMOS integrated circuit (IC) device embodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

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