Batch assembly of high density hermetic packages for power...

Details Batch assembly of high density hermetic packages for power... Batch assembly of high density hermetic packages for power...

H - Electricity

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H01L 21/52 (2006.01) H01L 21/50 (2006.01) H01L 21/60 (2006.01) H01L 23/04 (2006.01) H01L 23/538 (2006.01)

Patent

CA 2080690

Batch assembly methods for high density packaging of power semiconductor chips (32) in hermetic thin packaging include providing silicon chip arrays with thermocompressively bonded-foil contacts (38), preparing ceramic lid arrays (10) which contain upper surface and lower margin direct-bonded copper coverings (18) and through- the-lid high current spherical conductors (16), coining Cu/Mo/Cu or copper cup arrays (44), die mounting within each respective cup a respective semiconductor chip (32), su- perpositionally registering a lid array (10) with a strip form of cup array, and solder (21) reflowing to hermetically seal as hermet- ic thin packaging within a registered set of cup (44) and lid arrays (10).

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