Circuits for scrambling and descrambling packets and methods...

Details Circuits for scrambling and descrambling packets and methods... Circuits for scrambling and descrambling packets and methods...

H - Electricity

04

L

H04L 9/28 (2006.01) H04L 12/56 (2006.01) H04L 25/03 (2006.01)

Patent

CA 2386774

A circuit for descrambling a packet transmitted from and received in a communication device, includes (a) a plurality of descramblers (1-18 to 1-26) each receiving words obtained by developing the packet in parallel and descrambling data in the words to be descrambled, each of the descramblers being associated with a combination of addresses of the data in the words, (b) a padding number detector (1-7) which counts a padding number of a final word among the words, based on data indicative of a packet length which data is included in the packet, and (c) a data selector (1-36) which selects one of outputs transmitted from the descramblers in association with the combination to thereby receive data obtained by descrambling the words, from the thus selected descrambler.

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