Systems and methods for validating power integrity of...

Details Systems and methods for validating power integrity of... Systems and methods for validating power integrity of...

G - Physics

01

R

G01R 31/3181 (2006.01) G01R 31/3193 (2006.01)

Patent

CA 2688716

A power integrity system executes one or more test algorithms, such as a suite of test software that may be written in low level language that is coupled with a test environment housing an integrated circuit and/or printed circuit board, in order to identify possible power integrity issues with the integrated circuit and/or printed circuit board. The comparison between the written and the read data into a memory is used to identify the possible power integrity problems.

L'invention concerne un système d'intégrité de puissance exécutant un ou plusieurs algorithmes de test, tels qu'une suite de logiciels de test qui peuvent être écrits en langage de bas niveau, qui est couplé à un environnement de test hébergeant un circuit intégré et/ou une carte de circuit imprimé afin d'identifier des problèmes d'intégrité de puissance possibles avec le circuit intégré et/ou la carte de circuit imprimé. On utilise la comparaison entre les données écrites et les données lues en mémoire pour identifier les problèmes d'intégrité de puissance possibles.

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