Vector processor using buffer for preparing vector data

Details Vector processor using buffer for preparing vector data Vector processor using buffer for preparing vector data

G - Physics

06

F

354/237, 354/230

G06F 9/312 (2006.01) G06F 9/38 (2006.01) G06F 15/78 (2006.01)

Patent

CA 2000376

- 15 - ABSTRACT OF THE DISCLOSURE In a vector processor, a decoder generates a load request signal if an instruction stored in an instruction register is a vector load instruction and causes the instruction to be transferred to a stack. A resource manager has a plurality of flags associated respectively with vector registers provided in a calculation circuit and constantly updates the flags in accordance with contents of the associated vector registers. A contention detector is responsive to a vector load instruction being loaded into the stack for generating a proceed-to-transfer signal if no contention is detected between the vector load instruction and a corresponding flag in the resource manager. A buffer is provided in a memory controller for storing vector data from the memory in response to the load request signal from the decoder and transferring it to the calculation circuit in response to the proceed-to-transfer signal from the contention detector.

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