Method & apparatus for real-time data processing

Details Method & apparatus for real-time data processing Method & apparatus for real-time data processing

G - Physics

06

F

G06F 15/78 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2725130

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching intercon-nections of the hardware units.

La présente invention concerne un jeu d'instructions amélioré et la conception centrale, la commande et la communication de microprocesseurs programmables, impliquant la stratégie de remplacement du séquencement de programmes centralisés à l'heure actuelle et des processeurs en l'état de la technique par un nouveau séquencement de programmes distribués; chaque unité fonctionnelle possède son propre bloc d'extraction et de décodage d'instructions et chaque unité fonctionnelle possède sa propre mémoire locale destinée au stockage des programmes. Les unités d'exécution et les unités de mémoire du matériel informatique sont mises en pipeline flexible sous forme de processeurs intégrés programmables avec les étapes de pipeline reconfigurable d'un ordre différent en réponse à diverses séquences d'instructions d'application qui établissent les différentes configurations et les interconnexions de commutation des unités matérielles.

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