Method and apparatus for debugging a multicore system

Details Method and apparatus for debugging a multicore system Method and apparatus for debugging a multicore system

G - Physics

06

F

G06F 11/267 (2006.01)

Patent

CA 2635748

Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.

L'invention porte sur des techniques de débogage d~un système multicoeur à arrêt synchrone et reprise des capacités. Dans une exécution, l~appareil (par exemple un ASIC) comporte un premier et un deuxième coeur de traitement qui pendant le débogage reçoivent un ordre logiciel de s~arrêter et d~émettre un premier signal indiquant l~arrêt. L~autre coeur de traitement reçoit ce premier signal et s~arrête. Les deux cAEurs s~arrêtent quasiment ensemble suite au premier signal. Le premier et le deuxième signal peuvent être émis ou non par le même coeur de traitement.

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