Synchronous digital communication system with a hierarchical...

Details Synchronous digital communication system with a hierarchical... Synchronous digital communication system with a hierarchical...

H - Electricity

04

L

H04L 12/28 (2006.01) H04J 3/06 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2166036

In synchronous digital communication systems using a synchronization quality marker (SSM), timing loops can be created. To avoid such timing loops, a synchronous digital communication system is provided having network elements (NE11, ..., NE33) in which two classes (top, bottom) are defined for interface units (Sl, ..., Sx, ..., Sx+i).

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