Fault tolerant processing section with dynamically...

Details Fault tolerant processing section with dynamically... Fault tolerant processing section with dynamically...

G - Physics

06

F

G06F 11/16 (2006.01) G06F 11/18 (2006.01) G06F 11/20 (2006.01)

Patent

CA 2068048

- 75 - Abstract of the Disclosure A fault-tolerant digital data processor includes three identical logic CPU boards connected to a voting bus and a system bus. The three boards are initially designated as a master board, a slave board 0 and a slave board 1. The master board drives the system bus and the two slave boards serve as backups in case the master breaks. The master board issues signals, at different instances with the aid of multiplexing, to the slave boards. On the slave boards, corresponding signals are compared and the result is broadcast to all three boards. When all three boards are compared equal, the master board remains as master. If there is a miscompare between one slave board and the master but not between the other slave board and the master, the master board remains master, and the slave board with which the miscompare occurred will be disabled after another miscompare. If a miscompare occurs between the master board and both slave boards, a re-execution of the previous cycle occurs. After a master board failure is confirmed, a slave board becomes a master board, and if there is another comparison failure the former master board is disabled.

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