Integrable clock obtaining circuit

Details Integrable clock obtaining circuit Integrable clock obtaining circuit

H - Electricity

04

L

H04L 7/033 (2006.01) G06F 1/04 (2006.01) H03L 7/07 (2006.01) H03L 7/081 (2006.01) H04L 7/00 (2006.01)

Patent

CA 2196998

A method and a completely integrable circuit arrangement are proposed for recovery of a timing signal from a data stream. Two groups of phase regulators are supplied with a locally existing reference timing signal, preferably in each case one of mutually complementary reference timing signals. One phase regulator is each case, which has assumed a state within its operating range, is selected to provide the recovered timing signal, while a phase regulator which is currently not selected in kept in the state within its operating range which is diametrically opposite to the state of the currently selected phase regulator. On reaching the limit of the operating range of the currently selected phase regulator, a changeover is made to the phase regulator which has been kept ready until this point.

L'invention concerne un procédé et un circuit pouvant être entièrement intégré, servant à extraire le signal d'horloge d'un flux de données. Un signal d'horloge de référence disponible localement (de préférence l'un des signaux d'horloge de référence complémentaires) est acheminé vers deux groupes de déphaseurs. Chaque déphaseur occupant un état à l'intérieur de sa plage de fonctionnement, est sélectionné pour mettre à disposition le signal d'horloge extrait, tandis qu'un déphaseur non sélectionné est maintenu à disposition, à l'intérieur de sa plage de fonctionnement, dans un état diamétralement opposé à l'état du déphaseur sélectionné. Lorsque la plage de fonctionnement du déphaseur sélectionné atteint sa limite, on commute sur le déphaseur maintenu jusqu'alors à disposition.

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