Method of using electronically reconfigurable gate array...

Details Method of using electronically reconfigurable gate array... Method of using electronically reconfigurable gate array...

G - Physics

06

F

354/1

G06F 19/00 (2006.01) H03K 19/00 (2006.01)

Patent

CA 2025096

A plurality of electronically reconfigurable gale array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Des circuits logiques du type matrice électroniquement reconfigurable (MER) sont joints par le biais d'une interconnection reconfigurable, avec lesquels on peut représenter sous forme matérielle des réseaux numériques de grandes dimensions, par reconfiguration temporaire. Cette interconnection permet de changer à volonté le réseau numérique modélisé par les circuits interconnectés, de sorte que le système s'adapte à une bonne gamme de situations, en particulier des simulations, des essais de prototype, du calcul ou de l'exécution de procédures. L'interconnection reconfigurable peut comprendre un noeud formé de circuits MER servant uniquement aux fonctions d'interconnection, dans lequel cas chaque interconnection MER est reliée à au moins un contact (mais pas à tous) des circuits logiques. On décrit également d'autres plans d'interconnections reconfigurables.

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