Three-dimensional packaging technology for multi-layered...

Details Three-dimensional packaging technology for multi-layered... Three-dimensional packaging technology for multi-layered...

H - Electricity

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H01L 23/528 (2006.01) G11C 5/00 (2006.01) G11C 5/06 (2006.01) H01L 21/98 (2006.01) H01L 23/467 (2006.01) H01L 23/538 (2006.01) H01L 25/065 (2006.01) H01L 25/18 (2006.01) H05K 7/20 (2006.01) G02B 6/43 (2006.01)

Patent

CA 2338335

Disclosed is method and apparatus (1) for packaging multilayered integrated circuit (IC) chips (2), on which logic circuits and/or memory arrays are disposed and interconnected in a novel way permitting the addressing (i.e. selection) of the logic circuits and/or arrays on these IC chip layers using a minimum number of connections and with the shortest propagation delays.

L'invention concerne un procédé et un appareil (1) d'assemblage de microcircuits intégrés (2) sur lesquels les circuits logiques et/ou les mémoires sont disposés et interconnectés de manière innovatrice ce qui permet l'adressage (p. ex. la sélection) des circuits logiques et/ou des mémoires sur ces couches de microcircuits intégrés au moyen d'un nombre minimum de connexions et dans les délais de propagation les plus brefs.

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